Running multiple testbenches for VHDL designs
Running multiple testbenches for VHDL designs Whenever I create a VHDL design I tend to have many modules. Each of these modules are then connected to one main file and so everything is synthesised. But I want to write seperate test benches for each of these modules and one for the global process. It would be nice if I could do something to link all of these testbenches together and make them run in succession, to test my entire design in one run. How could I do this? I like to use GHDL and asserts. Is it possible to create one super-testbench? Or would a shell script which iterates over them be better? Good strategy. There are unit testing tools for VHDL too ... one called VUnit for example : github.com/LarsAsplund/vunit – Brian Drummond Jan 23 '16 at 23:20 @Paebbels, you are right. F...